Hi, I am thinking of doing a 76 pin 0.5x0.5 slot for run 3. To my understanding is that the project template ( https://mithro.github.io/gf180mcu-project-template/ ) isn't authoritative, in the event this doesn't match the expected power placement is there a list/discussion I can refer to for the power pin placement ?(edited)
I was re-reading the entire thread (as one does (to decided if I know enough to offer to design the 76 0.5x0.5 CoB PCB that has yet to exist)) and I am actually a little concerned about the vias in the encapsulation region.
Are we really sure this is okay ?
Open vias should not be used in the encapsulation area of the COB design due to
capillary wicking and leakage.
Though I really don't know enough about "why" this is a bad idea to judge if this applies to us and if namibj is correct.
5:03 a.m.
Will be independently taking a look at Chip on board technologies for multichip modules for the reason tomorrow as it is given as the source for this statement in that document.
Essen
I was re-reading the entire thread (as one does (to decided if I know enough to offer to design the 76 0.5x0.5 CoB PCB that has yet to exist)) and I am actually a little concerned about the vias in the encapsulation region.
Are we really sure this is okay ?
Open vias should not be used in the encapsulation area of the COB design due to
capillary wicking and leakage.
Interesting! These came from @Andrew Wingate‘s original 1x1 design, which did have some issues with bubbles as I understand it. But we thought that was most likely due to the vias not being covered by soldermask on top.
I don’t know if there’s a good reason why they are plated through holes instead of vias.
7:54 a.m.
I think the offer of CoB bonding is normally only available if you use the standard template, though that does make it a bit strange that the bonding is the same price for quarter slot as I thought it was ~priced per bond. Worth checking with Tim though if you want to make your own CoB.
1
RebelMike
Interesting! These came from @Andrew Wingate‘s original 1x1 design, which did have some issues with bubbles as I understand it. But we thought that was most likely due to the vias not being covered by soldermask on top.
I don’t know if there’s a good reason why they are plated through holes instead of vias.
I don’t know if there’s a good reason why they are plated through holes instead of vias.
Partially an inherited artifact if I remember, and also a quirk of KiCad that you can't have vias in a footprint if I remember.
1
RebelMike
I think the offer of CoB bonding is normally only available if you use the standard template, though that does make it a bit strange that the bonding is the same price for quarter slot as I thought it was ~priced per bond. Worth checking with Tim though if you want to make your own CoB.
I don't think we've gotten any of the quarter slot yet so don't have good pricing info on it yet, and am not certain prices really have to do with number of bonds directly, it's just a helpful tool to get you in the ballpark.
I'm also not certain we will be accepting any custom cob this time? Keep in mind the only custom ones last time shared the wirebonding layout, just had different traces and routing on the pcb.
1
Andrew Wingate
I don’t know if there’s a good reason why they are plated through holes instead of vias.
Partially an inherited artifact if I remember, and also a quirk of KiCad that you can't have vias in a footprint if I remember.
If there’s no particular reason for them then maybe it would be best to switch to vias - the extra clearance on them is a bit of a pain and it sounds like it would be safer to have no holes.
RebelMike
If there’s no particular reason for them then maybe it would be best to switch to vias - the extra clearance on them is a bit of a pain and it sounds like it would be safer to have no holes.
Yeah, they can be taken out.
Keep in mind part of the large clearance was the assumption the dies would be 0.7mm thick. It's still too early to assume that wouldn't be the case moving forward.
RebelMike
I think the offer of CoB bonding is normally only available if you use the standard template, though that does make it a bit strange that the bonding is the same price for quarter slot as I thought it was ~priced per bond. Worth checking with Tim though if you want to make your own CoB.
Yeah, if the 76 pin option is part of the "standard offering" is a bit unclear. Though frankly I am not opposed to paying the extra 2c per chip bond price increase if the maximum bonds budgeted for is 74 (1x1).
As far as I’m aware the standard offering is using the project template and standard CoB pad frame only so you only get 56 pins/48 IOs on the quarter slot. But if you need something different then I’m sure it’s worth talking to Tim
2
Essen
Yeah, if the 76 pin option is part of the "standard offering" is a bit unclear. Though frankly I am not opposed to paying the extra 2c per chip bond price increase if the maximum bonds budgeted for is 74 (1x1).
So sad ... I will ask Tim after Tawain to know what extra cost I would be looking at.
Else I guess I am doing 6 ports for the second generation switch rather than 8.
3:37 p.m.
In regards to adding vias it seems that there is a real concern is with wire displacements due to rapid changes in rheology during the oven-cure process ( reducing yield ).
source: Chip on Board: Technologies for Multichip Modules. Van Nostrand Reinhold, 1994, chapter 7(edited)
3:38 p.m.
In regards to this issue it seems like it would be problematic for vias under the wires rather than the ones in the corner.
We've done a lot of work to improve all the processes.
The PTH didn't seem to be a problem, rather the vias that were tented on the back side (there is no soldermask on the front)
We have ordered a number of untented versions, but I have been absent from that process for some time.
1
Andrew Wingate
We've done a lot of work to improve all the processes.
The PTH didn't seem to be a problem, rather the vias that were tented on the back side (there is no soldermask on the front)
We have ordered a number of untented versions, but I have been absent from that process for some time.
The epoxy is clear so you can see everything.
Any issues I'm referring to now are likely more cosmetic than anything.
Again, any of the bubbles I saw at the end were the amount of air trapped inside of a 0.25mm via. And the only reason you'd ever even know they were there is because it's clear. Everything is encased.
Andrew Wingate
The epoxy is clear so you can see everything.
Any issues I'm referring to now are likely more cosmetic than anything.
Again, any of the bubbles I saw at the end were the amount of air trapped inside of a 0.25mm via. And the only reason you'd ever even know they were there is because it's clear. Everything is encased.
Please don't understand this wrong way, I am not looking to impose my views on anyone, but in all transparency, the more I read the more I am personally concerned about the presence of holes in the encapsulation region.
5:16 p.m.
Currently I am concerned about 2 failure modes, short term: mechanical failure of the bond (lower yield), long term: corrosion(edited)
Maybe I'm misinterpreting what you're referring to as holes.
The die and the wires are all encapsulated.
Parts of the pcb are exposed because it's the pcb. There's a large mezzanine and caps on the back
Andrew Wingate
Maybe I'm misinterpreting what you're referring to as holes.
The die and the wires are all encapsulated.
Parts of the pcb are exposed because it's the pcb. There's a large mezzanine and caps on the back
I am currently using the following definition:
hole = any opening though the substrate (pcb) in which could form a contact between the epoxy and the air(edited)
Andrew Wingate
Maybe I'm misinterpreting what you're referring to as holes.
The die and the wires are all encapsulated.
Parts of the pcb are exposed because it's the pcb. There's a large mezzanine and caps on the back
Note the versions with soldermask between the pads and the die are the newer ones I did. As far as I’m aware Andrew hasn’t looked at those yet and they haven’t been made/tested. The 1x1 and the previous rev of the 1x0p5 have no solder mask in the region between the pads and the die - that led to vias that were closed on the back side but not the top side.
6:21 p.m.
On the CoBs I designed - I don’t really have any expertise here, I just wanted to help out as best I could as wafer space had offered me space on the early runs for free and Andrew was short on time. It sounds like changing those holes to vias would be wise - I’ll do that when I get chance!(edited)
1
Essen
Yeah, if the 76 pin option is part of the "standard offering" is a bit unclear. Though frankly I am not opposed to paying the extra 2c per chip bond price increase if the maximum bonds budgeted for is 74 (1x1).
The cost complication is with the bond house setup and test-run-overhead costs of setting up and verifying the custom/new bonding does actually work.
1
Essen
I am currently using the following definition:
hole = any opening though the substrate (pcb) in which could form a contact between the epoxy and the air (edited)
Oh, well, the epoxy to the top surface of the glob is AIUI less thickness.
6:35 p.m.
My understanding of the experienced bubble complication was with holes being tented on only the backside (where the mezzazine is) and being open on the front (where the die is), which had the air bubbles from inside escaping up into the epoxy.
1
RebelMike
On the CoBs I designed - I don’t really have any expertise here, I just wanted to help out as best I could as wafer space had offered me space on the early runs for free and Andrew was short on time. It sounds like changing those holes to vias would be wise - I’ll do that when I get chance! (edited)
I think I'm more worried about tented vias than fully open ones at least if they're thin enough for the epoxy to not just drip down; though it already stays in a glob up top anyways, so yeah.....
For reliability IMO we should at least ask if they have a generic CTE-vaguely-matched loaded version available given that I don' think they'd require actually different processing beyond dosing the epoxy from the other dispenser.
Might be contingent on the tracability serial being included, though; in case they fall down after globbing and are all mixed up between projects somehow.
Also while you're at it and worrying about those things, maybe see if the die bottom could have thermal management improved for allowing a higher TDP.
( I would be curious about running a mini testing program, more specifically a subset of the IPC-SM-789 torture test mentioned in “‘Guidelines for Chip on Board Technology implementation” on my end but I don't want to create duplicates )(edited)
Essen
Nice, what kind of electrical testing do you guys do ? (edited)
Are these a random sample of chips or are these all the chips that have been reported as some point as having failed packaging and is this an analysis of the failure modes ?
Essen
Are these a random sample of chips or are these all the chips that have been reported as some point as having failed packaging and is this an analysis of the failure modes ?
1
1
1
1
1
1
